| 基于FPGA的双倍率动态存储器读写误码检测仪的实现 |
| |
| 引用本文： | 陈康. 基于FPGA的双倍率动态存储器读写误码检测仪的实现[J]. 福州大学学报(自然科学版), 2011, 39(4): 546-549 |
| |
| 作者姓名： | 陈康 |
| |
| 作者单位： | 福州大学电气工程与自动化学院; |
| |
| 基金项目： | 福建省科技重大专项资助项目(2009HZ0007-1) |
| |
| 摘 要： | 针对硬盘缓存在高速读写时出现的误码问题,采用软硬件结合的方法(FPGA与单片机),通过FPGA同频异相时钟,实现了对不同厂商的双倍率内存可靠读写比较从而找到特定代码作为生产测试代码,实现对内存的低成本高效的检测.
|
| 关 键 词： | 检测仪 DDR FPGA VHDL 时序约束 时钟 |
DDR DRAM error code tester design based on FPGA |
| |
| CHEN Kang. DDR DRAM error code tester design based on FPGA[J]. Journal of Fuzhou University(Natural Science Edition), 2011, 39(4): 546-549 |
| |
| Authors: | CHEN Kang |
| |
| Affiliation: | CHEN Kang(College of Electrical Engineering and Automation,Fuzhou University,Fuzhou,Fujian 350108,China) |
| |
| Abstract: | This article mainly discusses the reliable way of reading,writing and compare the data in DDR DRAM from different vendors by single chip and FPGA to solve the miscompare error in hard disk production.Also the special different phase clock is used to get more stable result. |
| |
| Keywords: | tester DDR FPGA VHDL timing constraint clock |
| 本文献已被 CNKI 等数据库收录！ |
| 点击此处可从《福州大学学报(自然科学版)》浏览原始摘要信息 |
|
点击此处可从《福州大学学报(自然科学版)》下载免费的PDF全文 |
