| ADSP-TS101高速全双工Link收发器FPGA设计 |
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| 引用本文： | 王鹏,连帅彬,孙秋菊,黄文霞,钟莉娟.ADSP-TS101高速全双工Link收发器FPGA设计[J].信阳师范学院学报(自然科学版),2015(2):259-262. |
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| 作者姓名： | 王鹏 连帅彬 孙秋菊 黄文霞 钟莉娟 |
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| 作者单位： | 信阳师范学院物理电子工程学院;中国空空导弹研究院航空制导武器航空科技重点实验室 |
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| 基金项目： | 航空科学基金项目(20130112002);河南省教育厅自然科学研究计划项目(2011B510015) |
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| 摘 要： | 提出并实现了一种基于ADI Tiger SHARC101 Link协议的高速通信收发器TPGA设计方案,能同时在接口时钟的上升沿和下降沿收发数据,进而实现FPGA与DSP、以及FPGA片间的无缝连接.经ISE综合与布局布线验证,整个系统仅占用452个Slice,最高工作频率超过300 MHz,数据传输率可达4.8 Gb/s.
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| 关 键 词： | 高速通信 Link协议 双倍速率传输 数据收发器 |
Design of ADSP-TS101 High-Speed Full-Duplex Link Transmitter FPGA |
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| Wang Peng;Lian Shuaibin;Sun Qiuju;Huang Wenxia;Zhong Lijuan.Design of ADSP-TS101 High-Speed Full-Duplex Link Transmitter FPGA[J].Journal of Xinyang Teachers College(Natural Science Edition),2015(2):259-262. |
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| Authors: | Wang Peng;Lian Shuaibin;Sun Qiuju;Huang Wenxia;Zhong Lijuan |
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| Institution: | Wang Peng;Lian Shuaibin;Sun Qiuju;Huang Wenxia;Zhong Lijuan;College of Physics & Electronics Engineering,Xinyang Normal University;Aviation Key Laboratory of Science & Technology on Airborne Guided Weapons,China Airborne Missile Academy; |
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| Abstract: | A high-rate transceiver FPGA strategy based on ADI Tiger SHARC101 Link protocol was presented,which can complete data exchange both on rising edge and falling edge of interface clock,The seamless connection between FPGA and DSP / FPGA was achieved. After ISE synthesis and routing,the highest work clock of whole system can achieve 300 MHz,with only 452 slices utilized. The equivalent transmitting rate was 4. 8 Gb / s. |
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| Keywords: | high-rate communication Link protocol double date rate transmission data transceiver |
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