大整数除法器硬件电路研究与实现

为加快传统的大整数除法的运算速度，提出了一种适合硬件实现的低功耗大整数除法快速算法，在此基础上设计了一个低功耗大整数除法器硬件电路:将2个大整数分别存储在独立的随机访问存储器中，结合控制器和状态机，以实现高速数据读取和计算.所提出的除法器具备高速和低功耗特性，且支持多种位宽的除法以及求模运算，最高可支持4 096位的被除数以及2 048位的除数.使用130 nm CMOS工艺，从面积、功耗和速度方面对大整数除法器硬件电路进行分析，结果表明:该除法器的主频最高可达125 MHz，总面积为0.12 mm2，每兆赫兹消耗的功耗为10 μW.

Implementation of the Hardware Circuit for Big Integer Divider

In order to speed up the operation of traditional large integer division algorithm, a fast low-power algorithm is proposed for big integer division, which is suitable for hardware implementation, and a hardware circuit for the low-power divider is designed. Two big integers are stored in independent random-access memories and combined with the controller and the state machine to realize high-speed data reading and calculation. The proposed divider has the characteristics of high speed and low power consumption. The circuit can support multiple bit width division and modulus calculation as well as up to 4096-bit dividend and 2048-bit divisor. The proposed divider is evaluated and verified using a 130 nm CMOS process in the aspects of area, power consumption and speed. As the results show, the maximum frequency is 125 MHz, the area of the divider is 0.12 mm2 and the power consumption is 10 μw/MHz.