| 异步时序逻辑电路设计的一种简明方法 |
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| 引用本文： | 赵兴强. 异步时序逻辑电路设计的一种简明方法[J]. 西华师范大学学报(哲学社会科学版), 2004, 25(2): 227-230 |
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| 作者姓名： | 赵兴强 |
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| 作者单位： | 西华师范大学计算机科学系 四川南充637002 |
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| 摘 要： | 提出了一种异步时序电路设计的新方法：时钟信号与次态卡诺图联立法．根据时钟信号填写次态卡诺图，当触发器满足时钟信号时其次态由状态转换图决定，否则其次态为约束项．据此可方便求出驱动方程并判断自启动．
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| 关 键 词： | 异步时序逻辑电路 电路设计 时钟信号 次态卡诺图 状态转换图 约束项 |
| 文章编号： | 1001-8220(2004)02-0227-04 |
| 修稿时间： | 2004-02-13 |
Simple Method to Design Asynchronous Sequential Logic Circuit |
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| ZHAO Xing-qiang. Simple Method to Design Asynchronous Sequential Logic Circuit[J]. Journal of China West Normal University:Natural Science Edition, 2004, 25(2): 227-230 |
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| Authors: | ZHAO Xing-qiang |
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| Abstract: | This paper presents a new method to design asynchronous sequential circuit:clock signals and secondary state Karnaugy Map uniting method.A secondary Karnaugh Map is filled in based on clock signals,when the filp-flop satisfies the clock signals ,its state follows the state-shift map.If not ,the latter is a restrictive item.On these grounds ,drive equation can be easily deduced .Then we can judge whether the circuit can start automatically. |
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| Keywords: | asynchronous sequential logic circuit clock signals secondary state Karnaugh map. |
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