| 基于FPGA的IEEE1588频率合成模块的优化设计 |
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| 引用本文： | 颜丽,赵永平,黄莉雅.基于FPGA的IEEE1588频率合成模块的优化设计[J].萍乡高等专科学校学报,2013(3):79-82. |
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| 作者姓名： | 颜丽 赵永平 黄莉雅 |
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| 作者单位： | [1]萍乡学院,江西萍乡337000 [2]北京卫星环境工程研究所信息中心,北京100094 |
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| 摘 要： | 本文介绍了基于FPGA的IEEE1588频率合成模块的优化过程,通过重新构造关键路径的逻辑结构处理流程,将核心工作时钟频率从200Mhz提升到400Mhz使得输出10Mhz的精度从5ns提升到了2.5ns,基本满足高精度需求的使用场景。
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| 关 键 词： | 频率合成 FPGA IEEE1588 |
Optimization Design of IEEE1588 Frequency Synthesis Module Based on FPGA |
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| Yan Li;Zhao Yongping;Huang Liya.Optimization Design of IEEE1588 Frequency Synthesis Module Based on FPGA[J].Journal of Pingxiang College,2013(3):79-82. |
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| Authors: | Yan Li;Zhao Yongping;Huang Liya |
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| Institution: | Yan Li;Zhao Yongping;Huang Liya;Pingxiang University;Information Center,Beijing Institute of Spacecraft Environment Engineering; |
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| Abstract: | This paper introduces the process of optimizing IEEE1588 frequency synthesis module based on FPGA.By restructuring the process of logical construction of the key path,the core clock frequency is increased from 200 MHz to 400 MHz so that the precision of output 10 MHz is increased from 5ns to 2.5ns.It can basically meet usage scenarios which demand the high precision. |
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| Keywords: | Frequency Synthesis FPGA IEEE1588 |
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