空间辐射效应防护的标准单元库设计与实现

为提高空间环境下电子设备的可靠性，提升抗辐射加固SOI(Silicon on Insulator)集成电路的设计效率，通过构建完整的建库流程，自主设计开发了基于33 V 035 μm PD（Partly） SOI CMOS(Complementary Metal-Semiconductor)工艺平台,并面向Synopsys电子设计自动化软件的抗辐射加固标准单元库。标准单元采用H型栅及源漏非对称注入结构，以提高抗辐射性能，最后对该单元库进行了电子设计自动化工具流程验证和测试验证。实验结果表明，检错纠错验证电路功能符合设计要求，抗总剂量水平大于300 krad (Si)。

Design and Implementation of PD SOI CMOS Radiation-Hardened Standard Cells Library

To improve reliability of the electronic devices in space and efficiency of the radiation hardened SOI（Silicon on Insulator） ICs design, a library developing flow is established. The radiation-hardened standard cells library for Synopsys EDA（Electronic Design Automation) tools is designed based on 3.3 V-0.35 μm PD（Partly） SOI CMOS(Complementary Metal-Semiconductor) technology platform. The standard cells are composed of body contacted devices featuring H-gate， asymmetric source and drain to improve the radiation hardening performance. The cells library is validated by EDA tools and measurement. Experiments show that the EDAC(Error Detection And Correction) circuit functions properly with total dose of 300 krad (Si).