基于M算法的1000 BASE-T千兆以太网收发器联合解码均衡器实现研究

提出了一类适用于IEEE 802.3ab标准1000 BASE-T千兆以太网收发器的预滤波M算法联合解码均衡器.通过研究保留路径数、期望信道响应拖尾长度以及回溯深度等参数对M算法解码器的性能与硬件复杂度的影响,确定了优化参数和结构.0.18μm标准单元CMOS工艺下的综合和后仿真证明其性能与硬件复杂度均优于常用的预滤波并行判决反馈解码器(Parallel Deci-sion Feedback Decoder,PDFD).研究表明,预滤波M算法解码器适合在多种情况下取代预滤波PDFD,用于1000 BASE-T千兆以太网收发器联合解码均衡器,其中4tap PF-MA4解码器的性能优于14tap PDFD,而面积仅为其39%.

Design Consideration of M-algorithm Based Joint Trellis Decoder and Equalizer for 1000 BASE-T Gigabit Ethernet Transceiver

A class of pre-filtered M-algorithm(MA) decoder for IEEE802.3ab 1000 BASE-T Gigabit Ethernet(GbE) transceiver was proposed.By researching the influence of each architecture and parameter such as the number of remaining paths,pre-filter depth and trace-back depth to the performance and hardware complexity of MA decoder,the optimized parameters and architecture were decided.The physical design and post simulations indicate that the performance and hardware complexity are better than that of the classic pre-filtered parallel decision feedback decoder(PDFD).The results indicate that the pre-filtered MA decoder can be applied to 1000 BASE-T GbE transceiver application instead of pre-filtered PDFD in many cases.Especially,a four tap pre-filtered MA with four survival paths(MA4) achieves higher coding gain with 61% area saved when compared with 14tap PDFD.