| 基于FPGA自适应高速RS编译码器的IP核设计 |
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| 引用本文： | 李云鹏,谢显中,等.基于FPGA自适应高速RS编译码器的IP核设计[J].重庆邮电学院学报(自然科学版),2003,15(1):25-28,43. |
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| 作者姓名： | 李云鹏 谢显中 |
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| 作者单位： | [1]西安电子科技大学ISDN国家重点实验室，陕西西安710071 [2]重庆邮电学院移动通信工程研究中心，重庆400065 |
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| 基金项目： | 新一代野战网装备子项目“无线传输可靠性”资助 (YB- JM0 0 0 5 ) |
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| 摘 要： | 针对IP核设计方法讨论了一种可动态配置编码方案的高吞吐率RS编译码器，该编译码器采用Euclid算法实现译码，编译码过程采用流水线结构提高速率，整个设计使用VHDL语言描述，并在Xilinx公司的Virtex系列上实现验证。
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| 关 键 词： | FPGA 编译码器 Euclid算法 有限域乘法 IP核 流水线结构 VHDL语言 RS码 |
An IP Core Design for Reconfigurable Parameter High-Speed Reed-SolomonEncoder/Decoder on FPGA |
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| LI Yun peng,WANG Xin mei,XIE Xian zhong.An IP Core Design for Reconfigurable Parameter High-Speed Reed-SolomonEncoder/Decoder on FPGA[J].Journal of Chongqing University of Posts and Telecommunications(Natural Sciences Edition),2003,15(1):25-28,43. |
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| Authors: | LI Yun peng WANG Xin mei XIE Xian zhong |
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| Abstract: | This paper discusses a method of IP Core design for high performance Reed Solomon Encoder/Decoder, which has high throughput and can reconfigure coded parameter according to the channel changes in use. The Euclid Algorithm is used to implement decoding in this paper. Through pipeline, the latency of decoding process reduces dramatically.The whole design is described in VHDL, and implement verification is realized on Virtex family of Xilinx. |
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| Keywords: | Euclid algorithm finite field multiplier IP core pipeline VHDL |
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