A real-time 5/3 lifting wavelet HD-video de-noising system based on FPGA

In accordance with the application requirements of high definition ( HD) video surveillance sys-tems, a real-time 5/3 lifting wavelet HD-video de-noising system is proposed with frame rate conver-sion ( FRC) based on a field-programmable gate array ( FPGA) , which uses a 3-level pipeline par-alleled 5/3 lifting wavelet transformation and reconstruction structure, as well as a fast BayesShrink adaptive threshold filtering module.The proposed system demonstrates de-noising performance, while also balancing system resources and achieving real-time processing.The experiments show that the proposed system' s maximum operating frequency ( through logic synthesis and layout using Quar-tus 13.1 software) can reach 178MHz, based on the Altera Company' s Stratix Ⅲ EP3SE80 series FPGA.The proposed system can also satisfy real-time de-noising requirements of 1920 ×1080 at 60fps HD-video sources, while also significantly improving the peak signal to noise rate of the de-noising images.Compared with similar systems, the system has the advantages of high operating fre-quency, and the ability to support multiple source formats for real-time processing.