| 高速高效信道化接收机及其FPGA实现 |
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| 引用本文： | 栾文彬,唐丽.高速高效信道化接收机及其FPGA实现[J].应用科技,2008,35(2):13-16. |
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| 作者姓名： | 栾文彬 唐丽 |
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| 作者单位： | 哈尔滨工程大学,信息与通信工程学院,黑龙江,哈尔滨,150001 |
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| 摘 要： | 讨论了基于多相滤波器组的高速高效信道化接收机基本原理以及FPGA具体实现方案.该方案利用多相滤波的高效性和FFT的灵活性,大大降低运算速率和运算量,能够对前端上百兆带宽信号进行实时处理.系统仿真结果证明了该方法是对宽带信号具有全概率截获的能力.
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| 关 键 词： | 信道化 多相滤波 滤波器组 数字下变频 FPGA IP core 高速高效 信道化接收机 FPGA implementation efficiency high speed 能力 概率截获 宽带信号 方法 仿真结果 系统 实时处理 带宽 运算量 速率 活性 高效性 多相滤波器组 利用 |
| 文章编号： | 1009-671X（2008）02-0013-04 |
| 收稿时间： | 2007-05-28 |
| 修稿时间： | 2007年5月28日 |
The channelized receiver with high speed and efficiency and its implementation through FPGA |
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| LUAN Wen-bin,TANG Li.The channelized receiver with high speed and efficiency and its implementation through FPGA[J].Applied Science and Technology,2008,35(2):13-16. |
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| Authors: | LUAN Wen-bin TANG Li |
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| Abstract: | This paper discusses the basic principle of channelized receiver with high speed and efficiency based on polyphase filter and the actual implementation scheme of FPGA. This scheme greatly reduces the computational speed and overhead because of the efficiency of polyphase filter and the flexibility of FFT. It can achieve a real- time processing to forefront signals of 100MB bandwidth. Simulation indicates that the method has the capability of intercepting and capturing broadband signals with whole probability. |
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| Keywords: | channelization polyphase filter filter bank DDC FPGA IP core |
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