降低系统芯片测试时间的芯核联合测试方案

引入扩展的模式游程(x PRL)编码技术，通过无关位的动态传播策略以提高测试数据压缩效率.在此基础上，将系统芯片的多个芯核测试集联合为单一的测试数据流，用x PRL编码技术实施压缩，提出一种可重配置的串行扫描链结构，实现多核测试模式的联合应用.对嵌入6个大的ISCAS’89基准电路的样本系统芯片（SoC）应用建议的联合测试方案.结果表明，与传统芯核测试集独立压缩与应用技术相比，该方案不仅提高了测试数据的压缩性能，而且减少了扫描测试中的冗余移位和捕获周期，从而有效降低了SoC的测试应用时间.

A Core Union Test Scheme for Reducing System on Chip Test Time

An extended pattern run-length(x-PRL) coding approach was introduced,which uses a dynamic don't care bit propagation strategy to improve test data compression.Multiple core test sets for testing system on chip(SoC) are merged into a single data stream and compressed by the x-PRL coding.A reconfigurable serial scan chain was designed to make the test vectors of different cores union-applicable.The proposed scheme was applied to an example of SoC with six large ISCAS'89 benchmarks embedded.The(analysis) and e...