低功耗全流水线JPEG-LS无损图像编码器的VLSI设计

针对JPEG无损/准无损图像压缩标准(JPEG-LS)本身不利于并行计算和低功耗应用的问题,提出了一种JPEG-LS无损图像编码器的超大规模集成电路(VLSI)实现结构。它从功能上分为4部分:模式判别模块;时钟控制器;3条并行流水线;两级数据聚合器。这些模块以全流水线结构组织运算,能够达到实时图像处理的目的。4时钟域交叉并存,并包含专用时钟控制器的时钟管理机制,既保证瓶颈运算的进行,又能及时关断空闲模块的时钟,该措施使平均功耗降低了15.7%。该文提出的JPEG-LS编码器具有低功耗、高速图像处理的特征,已被应用于无线内窥镜系统。

VLSI design of a low power, fully pipelined JPEG-LS encoder for lossless image compression

A VLSI architecture was developed for lossless or near-lossless video compression in a JPEG-LS encoder by removing features that limit parallel computations and increase power consumption.The architecture includes a mode decision module,clock controller,3 linear parallel pipelines,and a two-tier data packer.Computations are fully pipelined in these modules for real time data processing.The clock management mechanism with 4 clock regions and a dedicated clock controller prevents bottlenecks in the calculations and shuts off the clocks in idle modules to reduce overall power consumption by 15.7%.The low power consumption,high data processing rate JPEG-LS encoder is being used in a wireless endoscopy system.