减少脉冲成形滤波器系数个数的高效算法

为了减小滤波器的复杂度、优化滤波的实时性，在不影响脉冲成形功能的前提下，提出了一种大幅缩减成形滤波器系数个数的算法。对比分析新算法设计出的滤波器与标准平方根升余弦滤波器时频特性的差异，在现场可编程逻辑门阵列（ FPGA）器件上实现这2类滤波器，并将新算法设计的成形滤波器运用到64？QAM通信系统中，利用Modelsim观察输入输出，发现脉冲成形效果良好，接收端信号星座图收敛迅速、聚类清晰，均验证了设计的可行性和有效性，表明采用新算法可以提高运算速度，减少FPGA实现的复杂度，节约硬件资源。

An efficient algorithm to reduce the number of pulse shaping filter coefficients

This paper proposed an algorithm to greatly reduce the number of filter＇s coefficients without damage to filter＇s performance, in order to reduce filter＇s complexity and optimize filter＇s instantaneity. The difference of time and frequency domain of pulse shaping filter using proposed algorithm versus standard root raised cosine filter meth？od was analyzed, and implementations on FPGA device were done. The designed pulse shaping filter was applied to a 64？QAM communication system. Using Modelsim to observe the I/O, good performance of pulse shaping was ob？tained, and the constellations of received signals were fast converged and clearly classified. The results above veri？fied the feasibility and effectiveness of the design, which indicates that the proposed algorithm can improve process？ing speed, reduce complexity of FPGA realization and save hardware resources.