分级式IC版图设计规则检查

针对层次式设计的集成电路版图，提出一种分级式的版图设计规则检查算法，通过提取和使用平时图形抽象，结合浮出重叠区覆盖下的子单元图形的方法，确定了各单元在任意布局下的设计规则检查运算２图形集，可以处理各种重叠情况。分级式ＤＲＣ分别对每个单元的ＤＲＣ图形集作一次检查，与打散式相比，大大减少了处理重复单元多的大规模，超大规模集成电路版图的工作量，从而缩短了检查时间，降低了内存需求，且更便于设计修改错误。

Hierarchical Design Rule Checking Approach for IC Layout

A new hierarchical design rule checking approach for hierarchical IC layout was proposed. Through extracting and using cell abstract, floating out son cell's overlaped graph in random overlapping case, the DRC operating graph set of each cell was obtained. This hierarchical DRC method can deal with complicated layout. It checks each cell's DRC graph set only once. In comparison with flat DRC, hierarchical one can save considerable memory and CPU time when there are a lot of repeated cells in the layout (this generally is true for LSI/VLSI), and is more covenient to designer for his correcting DRC errors.