ARM926EJ-S处理器中Cache一致性问题的探讨

在基于高性能ARM 处理器的SoC结构中，Cache致性问题是系统稳定运行的潜在威胁，消除该障碍是 系统设计师必须解决的问题。介绍了ARM926EJ-S处理器内Cache的工作原理以及基于该处理器的典型SoC结 构，重点论述了产生Cache致性问题的原因，并提出具体的解决方法。相关测试表明该方法切实可行，能够有效 避免数据不一致情况的发生，已被成功应用于课题项目中。

Study on Cache coherence in ARM926EJ-S processor

In the SoC architecture based on high performance ARM processor, cache coherence is a potential threat to stably running system, so the system designer must eliminate this obstacle. This paper introduces the principle of cache of ARM926EJ-S and describes the typical SoC architecture based on ARM processor. Furthermore, the paper presents the cause of cache coherence and the solution to this problem. The test shows that this method is feasible and can be used to avoid cache incoherence, which has already been applied successfully in corresponding project.