| 基于分级存储并行运算的FFT处理器设计 |
| |
| 引用本文： | 刘志哲,仲顺安. 基于分级存储并行运算的FFT处理器设计[J]. 北京理工大学学报, 2011, 31(6): 691-694 |
| |
| 作者姓名： | 刘志哲 仲顺安 |
| |
| 作者单位： | 北京理工大学信息与电子学院,北京,100081 |
| |
| 摘 要： | 研究了一种基于分级存储并行运算的改进快速傅里叶变换(FFT)处理器算法,通过减少对RAM存储器的读写次数降低功耗,采用并行运算方法减少数据处理时间.基于该算法以及改进的基-4蝶形单元设计了一款4096点FFT处理器.该处理器采用SMIC 0.18μm CMOS工艺设计实现,芯片核面积为9mm2,在slow工艺角条件下,版图后仿真最高时钟频率为192.3MHz,功耗为422mW@100MHz,最小处理时间为67.92μs.
|
| 关 键 词： | 快速傅里叶变换 分级存储 并行运算 |
| 收稿时间： | 2010-05-20 |
Design of FFT Processor Based on Grade-Memory and Parallel-Computation |
| |
| LIU Zhi-zhe and ZHONG Shun-an. Design of FFT Processor Based on Grade-Memory and Parallel-Computation[J]. Journal of Beijing Institute of Technology(Natural Science Edition), 2011, 31(6): 691-694 |
| |
| Authors: | LIU Zhi-zhe and ZHONG Shun-an |
| |
| Affiliation: | LIU Zhi-zhe,ZHONG Shun-an(School of Information and Electronics,Beijing Institute of Technology,Beijing 100081,China) |
| |
| Abstract: | The improved FFT arithmetic based on grade-memory and parallel-computation is proposed and studied.It can reduce the power consumption by decreasing the RAM’s writing-reading numbers as well as reduce the execution time by parallel-computation.A 4096-point FFT processor has been designed using the new arithmetic and the improved radix-4 butterfly.The processor was implemented by SMIC 0.18μm CMOS technology and the core area of the chip was 9mm2.In the slow corner condition,the post-layout simulation shows the highest frequency is 192.3MHz,the power consumption is 422mW@100MHz and the minimal execution time is 67.92μs. |
| |
| Keywords: | fast Fourier transform grade-memory parallel-computation |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
| 点击此处可从《北京理工大学学报》浏览原始摘要信息 |
|
点击此处可从《北京理工大学学报》下载全文 |
|
