一种采用时域比较器的低功耗逐次逼近型模数转换器的设计

基于CMOS 90 nm工艺设计了一款采用时域比较器的10位逐次逼近型模数转换器（successive approximation register analog-to-digital convertor，SAR ADC）.与传统动态比较器相比，时域比较器利用差分多级电压控制型延时线将电压信号转为时间信号，并通过鉴相器鉴别相位差而得到比较器结果，减小了共模偏移对比较器的影响和静态功耗.同时，电路采用部分单调式的电容阵列电压转换过程，有效减小电容阵列总电容及其功耗.仿真结果表明，在电源电压1 V，采样率308 kS/s，信号幅度0.9 V的情况下，有效位数（ENOB）为9.45 bits，功耗为13.48 μW. 

Design of Low-Power Successive Approximation Register Analog-to-Digital Convertor Based on a Time-Domain Comparator

In this paper, a 10 bit low power successive approximation register analog-to-digital converter (SAR ADC) was presented based on a time-domain comparator in 90 nm CMOS. Compared with conventional dynamic comparator, the time-domain comparator was arranged with differential multi-stage voltage controlled delay lines to convert voltage to time signal, and the time difference was sensed by a phase detector to reduce influence of common-mode various and static power consumption. And a partial monotonic switching strategy was employed to convert voltage in capacitor array, cutting down total capacitance and power consumption. Simulation results show that, with 1 V power supply, 308 kS/s at Nyquist sampling rate and 0.9 V signal scope, the ENOB can achieve 9.45 bit with 13.48 μW power consumption.