一种抗单粒子瞬态加固的压控延迟线设计

延迟锁相环中的压控延迟线是对单粒子事件（single event， SE）最敏感的子电路之一，其主要包括偏置电路和压控延时单元.利用双指数电流拟合3-D TCAD混合仿真中的单粒子瞬态（single-event transient， SET）电流，分析了压控延迟线对SE的敏感性.根据响应程度和电路结构的不同，对偏置电路进行了冗余加固；同时，对压控延时单元中提出了SET响应检测电路.在输入信号频率为1 GHz，电源电压1.2 V，入射粒子LET值为80 MeV·cm2/mg的条件下，Spice仿真表明:和未加固电路相比，偏置电压V_bn和V_bp在受到粒子轰击后，翻转幅度分别下降了75%和60%，消除了输出时钟信号中的丢失脉冲；设计出的检测电路能够将各种情况下有可能出现的SET响应指示出来，提高了输出时钟信号的可靠性. 

Radiation-Hardened by Design Techniques to Mitigate Single- Event Transients in Voltage-Controlled Delay Line

The voltage-controlled delay line (VCDL) is one of the most sensitive subcircuits to single event (SE) in delay-locked loops (DLLs),which consists of a bias circuit and voltage-controlled delay cells. The sensitivity of VCDL in a DLL to single-event transient (SET) was analyzed based on double exponential current source and 3-D TCAD mixed-mode simulation. According to the difference in the severity of SET response and circuit structure,the bias circuit was hardened by analog redundancy,while a SET detection circuit was proposed for voltage-controlled delay cells. Simulations,making under the condition of 80 MeV·cm²/mg linear energy transfer (LET) values,1.2 V supply voltage and 1 GHz input reference clock,show the perturbed magnitude of biasing voltages,V_bn and V_bp,can be significantly reduced by 75% and 60%,respectively,completely eliminating missing pulses of output signals compared with the unhardened one. The proposed detection circuit can indicate SET response in voltage-controlled delay cells under different circumstances,improving the reliability of output signals in the DLL.