一种并行结构有符号乘累加器的设计

本文采用补码分布式算法，简化了有符号数、无符号数以及混合符号数的乘加减运算，通过改进累加器树结构、全加器逻辑电路，设计了一种新型乘累加器结构。通过Altera公司的EP1C3T144C8实现了该乘累加器6个9位有符号操作数的乘累加运算的功能和时序仿真,结果证明了该算法的有效性。该设计解决了常规DA分布式算法系数不能更新和占用大量RAM资源的缺点，可以应用到数字滤波器设计中，也可以作为快速的运算单元应用到DSP数字信号处理器中。

Design of a parallel signed multiply accumulator

We employ complement distributed algorithm to simplify addition, subtraction and multiplication of signed number, unsigned number and the number with mixed symbols. We further design a new multiply accumulator structure through improving tree structure of an accumulator and logic circuit of a full adder. It is implemented with EP1C3T144C8 device from Altera company. Its effectiveness is proved through multiply accumulating functionality and timing simulation result of six nine bit signed operands. Its design overcomes the negatives of large RAM resource occupancy and no coefficient update of conventional distributed algorithm (DA). It can therefore be applied to the design of digital filters, and digital signal processors (DSP) as a rapid compute unit.