一种同步流水算术编码器的设计

针对JPEG2000标准中的算术编码器实现时,在上下文(CX)表更新、归一化及字节输出过程中具有返回或等待路径问题,提出一种新的同步流水算术编码器设计方案．该方案采用4步流水线设计,通过流水线操作的时序分析,得到了CX表的单步更新方法,并设计了一种树型搜索的寄存器的短延时0位检测电路．引入多路选择器来加速实现任意位左移,在提高主关键路径并行性的同时,采用了多种方法对寄存器传输级代码进行优化．实验表明,在EP1S258672C7上,最高工作时钟可达107．91MHz．

Design of New Pipeline Arithmetic Encoder

Focusing on the problem of path waiting or circular which existed in updating of context (CX) table and the renorme and byteout in the realization of the conventional arithmetic encoder in JPEG2000, a four-step pipeline architecture is employed to design an arithmetic encoder on FPGA platform to get high speed encoding. A new method of updating CX table is proposed ; and a new circuit with short delay is implemented to detect the left zeros of A-register. Multiplexers are adopted to accelerate the left shift operation, and parallel processing based on data dependency is used to optimize RTL(Register Transfer Language) code to shorten the main critical path. Experimental result shows that the encoder can work up to 107.91 MHz on Altera's EP1S25B672C7.