基于安全充分捕获技术的多时钟数字系统测试矢量生成

针对多时钟数字系统提出了一种新颖的产生测试矢量的方法——安全充分捕获技术(Safe and Complete Capture Technology,S&CCT).该方法对电路系统中的时钟按照一定的标准分为等效时钟和串行时钟，然后确定正确的时钟捕获顺序.使用并发故障模拟器从逻辑上和时序上对生成的测试矢量进行仿真，测试矢量生成器使用该仿真信息，以避免生成失效测试矢量.实验证明，S&CCT与传统方法相比，测试矢量数目减少50％左右，不仅大大减少了测试矢量的数目，对电路的硬件开销也几乎没有影响.

Automatic Test Pattern Generation for Multi-Clock Digital System Based on S&CCT

This paper presents a novel method of automatic test pattern generation for multi clock system, called S&CCT. The method classifies the system into equivalent clocks and serial clocks according to some regulations, and fixes the rightness of capture sequence. A concurrent fault simulator is used to simulate test vectors both on logic and timing in ATPG. The test vector generat or uses the simulating information, avoiding generating invalid vectors. Experiments show that S&CCT can reduce the number of test vectors by about 50% comparing with common methods, and has no influence on the cost of circuit hardware.