用于语音子频带编码的编解码器的设计与微处理机实现

本文基于Z-80微处理机设计并实现了一种适于语音子频带编码(SBC)的自适应差值脉码调制(ADPCM)编码器,在发送端,编码器把并行输入的16比特二进制数字信号压缩为3比特或4比特码字;在接收端,解码器将其恢复为原来的16比特,选择了最佳参数,3比特与4比特数编码分别能获得25和33分贝的信噪比,用不超过二十片集成电路实现的硬件编码器,以 Z-80A CPU作为算逻单元(4兆赫主频),对每一样值的处理时间小于3200个时钟周期,可接受的输入采样频率高于1200赫兹,能够用于语音(8000赫兹采样)八子频带实时编码,增加外部硬件乘法器可以大大提高编码器的处理速度,使可接受的输入采样频率大于4000赫兹,因此能够用于语音两子频带实时编码,文中对这种编码器的基本算法,阶步参数、计算机仿算和硬件实现进行了详细讨论。

Design and Microprocessor-Implementation of ADPCM Encoder for SBC

Designs and implements an adaptive differential pulse-code-modulation(ADPCM) system for encoding and decoding in the sub-band coding (SBC) system ofspeech,based on a Z-80 microprocessor. At transmitter the 16-bit binary digital signals are compressed as 3 or 4-bit codewords by an encoder,and then at receiver using a decoder to recover these codewords. With optimal parameters selected, the system offers a dynamic range of 40 db and the process signal-to-noise ratios attainable are 25 and 33db respectively for the 3 and 4-bit codings. Implementing with no more than 20 IC chips and taking a Z-80 CPU which operates at 4MHz clock frequecy as the ALU, the encoder can process each sample value in a duration about from 3000 to 3200 CPU clock cycles with an acceptable input signal frequency greater than 1200Hz. The system is thus available to the real-time coding of speech at 8 sub-bands(with sampling frequency 8000Hz). With the addition of multiplier hardware, the processing speed of encoder can be increased in so much that the acceptable input signal sampling frequency is greater than 4000 Hz and the system can thus be used for the rael-time coding of speech at two sub-bands. Discusses in detail the algorithm design, step-size parameters and IC implementation and analyzes the microcomputer simulation.