| 基于复杂可编程逻辑器件的数字频率计设计 |
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| 引用本文： | 潘明. 基于复杂可编程逻辑器件的数字频率计设计[J]. 广西科学院学报, 2002, 18(4): 244-247,251 |
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| 作者姓名： | 潘明 |
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| 作者单位： | 桂林电子工业学院计算机系,桂林,541004 |
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| 摘 要： | 选用在系统可编程大规模集成ispLS11032-70PLCC84芯片作硬件电路，以Lattice Expert7.1作EDA设计工具，设计一种新型数字频率计，该频率计采用ABEL－HDL对其中的各部分元器件进行编程，实现了闸门控制电路、计数电路、多路选择电路、位选电路、段选电路等。频率计的测频范围：1Hz-70MHz。该设计方案通过了软件仿真、硬件调试和软硬件综合测试。
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| 关 键 词： | 数字频率计 复杂可编程逻辑器件 硬件描述语言 设计方法 闸门控制电路 计数电路 |
| 收稿时间： | 2002-06-28 |
Design of Digital Cymometer Based on Complex Programmable Logic Device |
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| Pan Ming. Design of Digital Cymometer Based on Complex Programmable Logic Device[J]. Journal of Guangxi Academy of Sciences, 2002, 18(4): 244-247,251 |
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| Authors: | Pan Ming |
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| Affiliation: | Department of Computer, Guilin Institute of Electronic Technology, Guilin, 541004 |
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| Abstract: | Lattice Expert 7.1 is used successfully to make a new-type digital cymometer with a Complex Programmable Logic Device (CPLD) used as virtual kernel of the cymometer,and a large programmable logic device (ispLSI1032E) used as hardware circiuit. The one chip includes strobe control circuit,count circuit,multi-choice circuit,bit-choice circuit, segment-choice circuit which are designed by ABEL-HDL.The frequency is designed from 1 Hz to 70 M Hz. The whole system passes the debugging in software simulation, software and hardware parts. |
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