| PLD逻辑电路设计的CAD方法 |
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| 引用本文： | 马梅林.PLD逻辑电路设计的CAD方法[J].辽宁工程技术大学学报(自然科学版),1998,17(3):286-288. |
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| 作者姓名： | 马梅林 |
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| 作者单位： | 河北建筑科技学院!邯郸056038 |
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| 摘 要： | 介绍了可编程逻辑器件PLD在逻辑电路设计中的开发流程;论述了时序电路设计中状态最小化CAD方法,它能够依据原始状态表和初始化数据,自动完成状态最小化;实现逻辑图设计;为PLD的推广应用和新型状态机FSM的研制提供了方便。
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| 关 键 词： | PLD 逻辑电路 设计CAD |
The Method of CAD of Logic Circuit Design of PLD |
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| Ma Meilin,Liu Zenghuan,Wang Zhentao.The Method of CAD of Logic Circuit Design of PLD[J].Journal of Liaoning Technical University (Natural Science Edition),1998,17(3):286-288. |
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| Authors: | Ma Meilin Liu Zenghuan Wang Zhentao |
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| Abstract: | The article introduces briefly the developing flow of the programmable logic device PLD in the logic circuit design.describes the method of CAD of state minimization in time sequencing circuit design.lt can automaticaly accomplish state minimization according to the original state table and initialization data,realize the logic diagram design,providing convenience for the extensive application of PLD and the development of the new finite state machine FSM. |
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| Keywords: | state equivalence minimization programmable CAD |
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