| 一种Montgomery模乘算法硬件实现的改进电路 |
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| 引用本文： | 张怡浩,田则,于敦山,盛世敏.一种Montgomery模乘算法硬件实现的改进电路[J].北京大学学报(自然科学版),2004,40(1):80-84. |
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| 作者姓名： | 张怡浩 田则 于敦山 盛世敏 |
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| 作者单位： | 北京大学微电子学系，北京，100871 |
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| 摘 要： | 速度与面积是数字集成电路设计的两个重要目标，由于它们之间通常是一种相互制约的关系，所以往往要在一定程度上进行折中。作者提出的改进方法可以在几乎不增加硬件面积的条件下有效地提高速度。
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| 关 键 词： | Montgomery RSA VLSI硬件实现 |
| 收稿时间： | 2002-12-16 |
An Improvement in the VLSI Implementation of Montgomery Algorithm |
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| ZHANG Yihao TIAN Ze YU Dunshan SHENG Shimin.An Improvement in the VLSI Implementation of Montgomery Algorithm[J].Acta Scientiarum Naturalium Universitatis Pekinensis,2004,40(1):80-84. |
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| Authors: | ZHANG Yihao TIAN Ze YU Dunshan SHENG Shimin |
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| Institution: | Department of Microelectronics, Peking University, Beijing, 100871 |
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| Abstract: | Modular exponentiation of large operands is the kernel operation in many public-key cryptosystems,RSA algorithm for instance.Montgomery algorithm is often used as a solution.In the VLSI implementation of Montgomery algorithm,the speed is the top target. An improvement is proposed with little or even no increase in the hardware area but apparently saving much time. |
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| Keywords: | Montgomery RSA |
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