| Walsh—Hadamard变换ASIC的并行结构设计 |
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| 引用本文： | 周六丁,程代杰.Walsh—Hadamard变换ASIC的并行结构设计[J].重庆大学学报(自然科学版),1993,16(6):93-99. |
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| 作者姓名： | 周六丁 程代杰 |
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| 作者单位： | 重庆大学电子信息学院，重庆大学电子信息学院，重庆大学电子信息学院 重庆 630044，重庆 630044，重庆 630044 |
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| 摘 要： | 针对具有广泛应用的Ｗａｌｓｈ－Ｈａｄａｍａｒｄ变换，研究了适合其ＡＳＩＣ设计的算法与ＳＦＧ阵列结构、位串计算、可变长功能等方面的内容，并给出了Ｗａｌｓｈ－Ｈａｄａｍａｒｄ变换ＡＳＩＣ的一种合理结构。
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| 关 键 词： | 并行计算 W－H变换 ASIC 集成电路 |
Parallel Architectures of the ASIC for Walsh-Hadamard Transform |
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| Zhou Liuding Cheng Daijie Zou Hua.Parallel Architectures of the ASIC for Walsh-Hadamard Transform[J].Journal of Chongqing University(Natural Science Edition),1993,16(6):93-99. |
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| Authors: | Zhou Liuding Cheng Daijie Zou Hua |
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| Institution: | Zhou Liuding Cheng Daijie Zou Hua |
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| Abstract: | The design of ASIC (Application-specified Integrated Circuit) has been recently paid a lot of attention to by scholars. In this paper,investigation was made in some respects related with the design of the ASIC for Walsh-Hadamard transform (WHT). These respects include the desing of the dedicated algorithma and their SFGs(Signal Flow Graphs),the design of the VLSI array, bit-string computation, and variable-size function. At the end, resonable VLSI array architecture was presented for the WHT ASIC. |
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| Keywords: | algorithm architecture parallel computation walsh-Hadamard transform |
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