| 同步数字集成电路设计中的时钟树分析 |
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| 引用本文： | 殷瑞祥,郭瑢.同步数字集成电路设计中的时钟树分析[J].汕头大学学报(自然科学版),2005,20(3):75-80. |
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| 作者姓名： | 殷瑞祥 郭瑢 |
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| 作者单位： | 华南理工大学电子与信息学院,广东,广州,510640 |
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| 摘 要： | 研究了同步数字系统的组成和时钟偏移,并结合一个数字集成电路8051的时钟树设计实例,介绍了时钟树的经验结构和设计方法流程.比较了采用Synopsys公司的布局布线工具实现的自动时钟树分析与指定结构时钟树分析,证明结构恰当的时钟树能得到比自动时钟树分析更好的结果.
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| 关 键 词： | 同步数字系统 集成电路设计 时钟树分析 时钟偏移 |
| 文章编号： | 1001-4217（2005）03-0075-06 |
| 收稿时间： | 2004-11-18 |
| 修稿时间： | 2004年11月18 |
Clock Tree Synthesis in Synchronous Digital Integrated Circuit Design |
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| YIN Rui-Xiang,GUO Rong.Clock Tree Synthesis in Synchronous Digital Integrated Circuit Design[J].Journal of Shantou University(Natural Science Edition),2005,20(3):75-80. |
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| Authors: | YIN Rui-Xiang GUO Rong |
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| Abstract: | In the synchronous digital integrated circuits,the design of clock tree can dramatically affect system-wide performance and reliability. In this article, synchronous digital system and clock skew were introduced. A method to design clock tree was presented and used to design clock tree of 8051. The method compared the results of automatic clock tree synthesis and structure-specified clock tree synthesis performed by Astro. It is proved that the clock tree structure designed before can get better result than automatic clock tree synthesis. |
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| Keywords: | synchronous digital system integrated circuit design clock tree clock tree synthesis clock skew |
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