| Fault Tolerance Mechanism in Chip Many-Core Processors |
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| 作者单位： | Key Laboratory of Computer System and Architecture Institute of Computing Technology，Chinese Academy of Sciences，Graduate University of Chinese Academy of Sciences，Beijing 100080，China，Key Laboratory of Computer System and Architecture，Institute of Computing Technology，Chinese Academy of Sciences，Key Laboratory of Computer System and Architecture，Institute of Computing Technology，Chinese Academy of Sciences，Key Laboratory of Computer System and Architecture，Institute of Computing Technology，Chinese Academy of Sciences，Beijing 100080，China，Beijing 100080，China，Beijing 100080，China，Beijing 100080，China |
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| 基金项目： | 国家自然科学基金;国家重点基础研究发展计划(973计划);中国科学院科研项目 |
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| 摘 要： | As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N M is proposed to improve N-core processors' yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors' performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.
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Fault Tolerance Mechanism in Chip Many-Core Processors |
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| Authors: | ZHANG Lei HAN Yinhe LI Huawei LI Xiaowei |
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| Abstract: | As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N M is proposed to improve N-core processors'yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors'performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time. |
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| Keywords: | chip many-core processors yield fault tolerance reconfiguration network-on-chip |
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