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基于可见光图像和红外图像决策级融合的目标检测算法
引用本文:白玉,侯志强,刘晓义,马素刚,余旺盛,蒲磊. 基于可见光图像和红外图像决策级融合的目标检测算法[J]. 空军工程大学学报(自然科学版), 2020, 21(6): 53-59
作者姓名:白玉  侯志强  刘晓义  马素刚  余旺盛  蒲磊
作者单位:西安邮电大学计算机学院,西安,710121;西安邮电大学陕西省网络数据分析与智能处理重点实验室,西安,710121;空军工程大学信息与导航学院,西安,710077
基金项目:国家自然科学基金(61973280);中国博士后科学基金(2019M661069)
摘    要:针对目前NAND FLASH随着使用时间的增长误码率随之增高的特性,提出了一种在使用更少校验位的情况下纠错能力更强的高速并行RCRF+BCH纠错方案,初步用RCRF的思想对部分初始擦除错误进行纠正,然后级联BCH码纠正剩余的位错,很好地保证数据的准确性,显著提高存储系统的可靠性。首先详细阐述了该高速并行算法的编译码原理和执行步骤,在BCH部分中使用消耗更少硬件资源的无求逆的iBM关键方程求解算法,然后推导出错误位置多项式不同路径的几种确定形式,方便应用组合逻辑对其进行描述,避免了复杂的迭代判断过程,进一步提高了译码速度,并采用模块化的处理方式和流水线的操作模式优化了BCH的编译码结构。最终在FPGA平台硬件实现并仿真验证了此方案的有效性。

关 键 词:目标检测  YOLOv3网络  决策级融合  加权融合

An Object Detection Algorithm Based on Decision Level Fusion of Visible Light Image and Infrared Image
BAI Yu,HOU Zhiqiang,LIU Xiaoyi,MA Sugang,YU Wangsheng,PU Lei. An Object Detection Algorithm Based on Decision Level Fusion of Visible Light Image and Infrared Image[J]. Journal of Air Force Engineering University(Natural Science Edition), 2020, 21(6): 53-59
Authors:BAI Yu  HOU Zhiqiang  LIU Xiaoyi  MA Sugang  YU Wangsheng  PU Lei
Abstract:Aimed at the characteristic that the error rate of NAND FLASH increases with the increase of the time of use, a high speed parallel RCRF+BCH error correction scheme with stronger error correction capability while using fewer parity bits is proposed. The idea of RCRF corrects some of the initial erasure errors, and then cascades BCH codes to correct the remaining bit errors, which can greatly ensure the accuracy of data and significantly improve the reliability of the storage system. The article explains in detail the encoding and decoding principles and execution steps of the high speed parallel algorithm. In the BCH part, the iBM key equation solving algorithm without inversion that consumes less hardware resources is used, and then the different paths of the error position polynomial are listed through derivation Several-deterministic forms facilitate the application of combinatorial logic to describe them, thus avoiding the complicated iterative judgment process and further improving the decoding speed. And adopt the modular processing method and the pipeline operation mode to optimize the BCH codec structure. Finally, it was implemented on FPGA platform hardware and simulated to verify the effectiveness of this scheme.
Keywords:error correction system   Reset-Check-Reverse-Flag  N10Bose-Chaudhuri-Hocquenghem   NAND-FLASH
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