面向时序逻辑的门级信息流分析方法

利用门级信息流追踪逻辑基础理论,研究了门级信息流时序逻辑扩展问题,在确定系统时钟作为基础可信源情况下,给出了扩展4种典型触发器的实现方案.针对IWLS测试向量集使用Synopsys综合编译器,生成90 nm标准库文件,对门级信息流跟踪逻辑的面积、时间延迟和功耗等参数进行了评估.与未经优化的原始GLIFT编码相比,在引入时序逻辑之后,电路的平均面积消耗降低了50％以上,时间延迟减少13％左右,获得的面积和时间延迟信息反映了在逻辑门级层次上实现细粒度信息流控制的复杂性；而仿真获得的功耗对比结果表明追踪逻辑的功耗达到原始逻辑的5～20倍左右,功耗问题需要进一步研究和优化.

Gate Level Information Flow Control Research Based on Sequential Logic

The timing logic problem of gate-level information flow is investigated based on basic GLIFT theory, the implementation of four typical triggers is given when the system clock is trusted.The gate-level information flow tracking logic area, time delay and power consumption are evaluated for the test vectors of the IWLS set using Synopsys compiler to generate 90 nm standard library files. Compared with the original GLIFT code, the average area of the circuit is reduces more than 50%, time delay is reduces about 13% when timing logic is introduced. The obtained area and time delay information reflect the complexity of fine-grained control of information flow; the simulation results of power consumption comparison show that the power consumption of the tracking logic reaches about 5 to 20 times the original logic, the power consumption issues need further research and optimization.