体系结构级功耗分析方法

功耗问题已经成为集成电路设计，尤其是嵌入式系统和电池供电设备开发中所要关注的重要问题。电路设计较低层次的功耗分析方法能提供比较好的准确性，但它们的功耗模型相对复杂，功耗分析的时间开销和内存开销都很大。本丈所讨论的体系结构级功耗分析方法就克服了这些缺点，通过对可配置的功能单元分别进行功耗建模，基于准确的性能模拟来达到功耗模拟的目的，它可以广泛应用于体系结构、指令集、编译器以至软件的低功耗优化中，文章最后借助于通用CPU的系统级功耗模拟工具Wattch，研究了指令及数据缓存在配置方方法的功耗行为，实验证明，体系结构级的功耗分析为低功耗系统设计提供了更有价值的指导。

Power Analysis Methods in Architectural Level

Power has become an increasingly important issue in the design of integrated circuits, especially for embedded systems and battery-operated devices. Power analysis methods at lower design levels achieve very good accuracy, but they are very complicated, and the runtime and memory require are often very hard to accept. To deal with these problems, the power analysis method in architectural level is discussed. The method can obtain the aim of high-level power simulation by accurate cycle-by-cycle performance simulation, where the models of different functional modules are made separately. Architectural level power analysis makes the power optimization of architectural-level, instruction set level, compiler and software become possible. Experiments are set up by the use of Wattch, a general purposed CPU architectural-level power simulator, to demonstrate the power behavioral of data and instruction caches. The results show that power analysis at architectural level can guide the design of low-power system greatly.