基于ARM7TDMI 的I_cache controller设计

Cache,即高速缓冲存储器,是位于微处理器和主存之间规模小、速度快的存储器.提出了基于AR-M7TDMI核的指令cache控制器的设计方案和电路实现.主要采用verilog硬件描述语言对I—cache controller进行RTL描述,并用modelsim工具进行前端仿真,比较了嵌入式系统中有无I_cache的工作效率.结果表明,系统中加入I_cache电路以后存储性能会有显著提高.

Design of I_cache Controller Based on ARM7TDMI

Cache, namely the cache memory, which has the small scale and high speed, is located between the microprocessor and the main memory. This article proposes the design proposal and the electric circuit realization of the instruction cache controller , which are based on design characteristic of ARM7TDMI core. The verilog HDL are mainly used to behaviorally describe the I _ cache controller, and the tool of modelsim is used to carry on the front _ end simulation with the modelsim tool, and the working efficiency of the type system with I _ cache and without I _ cache is compared. The result indicates that when joining the I _ cache in the system the memory property is able to have the remarkable enhancement.