| （7＆#215;7）奇偶校验电路的EDA设计 |
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| 引用本文： | 严添明.（7＆#215;7）奇偶校验电路的EDA设计[J].淄博学院学报(自然科学与工程版),2014(1):58-64. |
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| 作者姓名： | 严添明 |
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| 作者单位： | 黎明职业大学信息与电子工程学院,福建泉州,362000 |
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| 摘 要： | 介绍了常用的水平垂直冗余校验码---（7＆#215;7）奇偶校验编码解码逻辑电路的EDA 设计，用V HDL语言对（7＆#215;7）奇偶校验编码器和解码器进行描述，用Quartus II软件进行仿真测试。从仿真结果看，电路完全符合要求，可以烧写成芯片。
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| 关 键 词： | 信道编码 奇偶校验 电路设计 EDA软硬件设计 |
Design of logic circuit for （7 ＆#215; 7） parity generators and checkers with EDA |
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| YAN Tian-ming.Design of logic circuit for （7 ＆#215; 7） parity generators and checkers with EDA[J].Journal of Zibo University(Natural Sciences and Engineering),2014(1):58-64. |
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| Authors: | YAN Tian-ming |
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| Institution: | YAN Tian-ming |
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| Abstract: | This paper introduces the design of logic circuit for （7 ＆#215; 7） parity generators and check-ers with EDA .It is a Longitudinal-Vertical Redundancy Check and is often applied in data trans-mission .The （7 ＆#215; 7） parity generators and checkers are simply described with VHDL language , and are simulated it with the software of Quartus II .The simulation results show that it can meet the requirements and can load chip . |
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| Keywords: | channel coding parity circuit designing EDA |
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