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基于模数混合的高速激光信号同步算法
引用本文:朱理辰,赵晨宁,王继超,安建平.基于模数混合的高速激光信号同步算法[J].系统工程与电子技术,2018,40(10):2157-2165.
作者姓名:朱理辰  赵晨宁  王继超  安建平
作者单位:1. 北京理工大学信息与电子学院, 北京 100081; 2. 中国船舶工业综合技术经济研究院, 北京 100081
摘    要:针对全数字环路在高速信号同步中的应用局限,提出了一种基于模数混合的同步算法。利用高速门电路和有源阻容(resistance capacitance, RC)积分电路完成高速模拟信号与再生信号的相关运算,经低速模数采样、插值计算、环路滤波处理,调整再生信号,形成模数混合的闭合环路,实现对传输时延的跟踪。仿真与分析结果表明,对于传输速率2.5 Gsps的宽带信号,Eb/N0高于-10 dB时,模数混合算法同步精度在80 ps以内,与全数字算法相当;同时,与全数字算法相比,此算法明显降低了采样率,大幅降低了数字信号处理运算复杂度,节约了时钟和处理资源,并降低了功耗,更适于高速传输系统。


Synchronization algorithm for high-speed laser signals based on analog-digital combination
ZHU Lichen,ZHAO Chenning,WANG Jichao,AN Jianping.Synchronization algorithm for high-speed laser signals based on analog-digital combination[J].System Engineering and Electronics,2018,40(10):2157-2165.
Authors:ZHU Lichen  ZHAO Chenning  WANG Jichao  AN Jianping
Institution:1. School of Information and Electronics, Beijing Institute of Technology, Beijing 100081, China); 2. China Institute of Marine Technology & Economy, Beijing 100081, China;
Abstract:In order to solve the application limitations of fully digital delay-locked loop (FDDLL) in high speed signal synchronization, this paper proposes a synchronization algorithm based on the combination of analog and digital domains. High speed gate circuits and active resistance-capacitance (RC) integrators are utilized to accomplish the correlation calculation between high speed analog signals and local regenerated signals. After sampling through low-speed analog to digital, interpolating, and loop filter, the digital output is used to estimate the transmitting delay, which is applied to adjust the regenerated signal. In this way, a closed synchronization loop mixed of analog and digital domains is generated, which can realize maintaining tracking of high speed signals. Both simulation and analysis results show that for the signal of transmission rate 2.5 Gsps, synchronization accuracy within 80 ps can be achieved through the proposed algorithm when Eb/N0 is higher than -10 dB, which is comparable to FDDLL. Meanwhile, compared with FDDLL, the proposed algorithm requires much lower sampling rate, which leads to a significant decrease of computational complexity of the digital signal processor. It saves clock and processing resources. Also power consumption is notably reduced through the proposed loop algorithm. It is more suitable for high speed transmission system.
Keywords:
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