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用于卫星载荷数据传输总线的终端IP核设计
引用本文:刘文婷,万小磊,徐楠,杨童,陈亮亮. 用于卫星载荷数据传输总线的终端IP核设计[J]. 应用科学学报, 2021, 39(2): 232-240. DOI: 10.3969/j.issn.0255-8297.2021.02.005
作者姓名:刘文婷  万小磊  徐楠  杨童  陈亮亮
作者单位:中国空间技术研究院 通信与导航卫星总体部, 北京 100094
基金项目:国家科技重大专项(No.2017ZX01013101-003)资助
摘    要:根据通信卫星有效载荷数据传输总线协议及其工作原理,提出了一种总线终端IP(intellectual property)核的设计及验证方法,该IP核由总线接口模块、时钟分频模块、协议处理模块、数据采集模块等组成,其设计和研制具有自主知识产权.该IP核完成了模块仿真验证、芯片系统仿真验证和FPGA(field progra...

关 键 词:通信卫星  载荷数据传输总线  IP核  总线终端  FPGA验证
收稿时间:2019-03-19

Design of the RT IP Core for Satellite Payload Data Bus
LIU Wenting,WAN Xiaolei,XU Nan,YANG Tong,CHEN Liangliang. Design of the RT IP Core for Satellite Payload Data Bus[J]. Journal of Applied Sciences, 2021, 39(2): 232-240. DOI: 10.3969/j.issn.0255-8297.2021.02.005
Authors:LIU Wenting  WAN Xiaolei  XU Nan  YANG Tong  CHEN Liangliang
Affiliation:Institute of Telecommunication and Navigation Satellites, China Academy of Space Technology, Beijing 100094, China
Abstract:Based on serial bus protocol, a remote terminal IP (intellectual property) core for satellite payload data bus is proposed. The IP core is composed of bus interface module, frequency divider module, protocol processing module and data collecting module. The IP core design is tested and verified by functional simulation and FPGA (field programmable gate array) test, and has been taped out successfully. Test results indicate that the designed IP core has good performance in capability, reliability and less resource occupancy. It can be used for testing the payload data bus in satellite systems or in verification equipment of satellite systems.
Keywords:communication satellite  payload data bus  IP (intellectual property) core  remote terminal  FPGA (field programmable gate array) test  
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