高速数字模块的层次化物理实现技术

针对深亚微米工艺下后端实现中布线资源紧缺这一难点提出了一种改进的层次化流程.通过考虑子电路在上层电路中的连接关系调整子电路的高宽从而优化布线资源并降低延迟.采用量化分析的方法一次性得到可实现的物理设计,避免了多次迭代尝试浪费的时间.以DSP中大规模多路选择器在SMIC 65nm low leakage工艺下的物理设计为例介绍了本文提出的优化方案,并且对比可得本文提出的方法能减少20%的面积和35%的延迟.

An Improved Hierarchy Physical Design Flow for High Speed Circuits

This paper proposed an improved hierarchical flow for physical design in deep sub-micron technology. This flow can reduce routing congestion and improve timing delay. The key point of this flow is to use the external connectivity information of the target block to design the floorplan, which could achieve a good place and route result in one iteration using quantitative analysis, saving time and efforts from multiple failed iterations. The proposed flow was tested on a large mux block in DSP design in SMIC 65 nm low leakage process, and the result showed it improved 20% in area and 35% in timing delay compared with the traditional flow.