基于多FPGA的片上网络模拟平台设计和实现

针对片上网络的设计和优化问题，提出了一种基于多FPGA的片上网络模拟平台结构，用于加速片上网络的功能验证和性能评估.通过层次化设计和分布式流量管理器等技术，有效地提高了系统的灵活性，加速了片上网络的设计空间搜索.实验结果表明，多FPGA模拟平台不仅相对于传统的软件仿真具有500~10 000倍的加速比，与其他片上网络模拟平台相比也具有明显的速度优势.

Design and Implementation of a Multi-FPGA Based Networks-on-Chip Emulation Platform

To address the design and optimization of Networks-on-Chip (NoC), a multi-FPGA based NoC emulation platform was proposed to speed up the functional verification and performance evaluation of NoC. By introducing hierarchical design approach and distributed traffic manager, the system flexibility is effectively improved while accelerating design space exploration (DSE) of NoC. The experiment result shows that the proposed emulation platform not only has a speedup of 500~10 000 times compared with classic software-based simulation method, but also outperforms other NoC platforms in emulation speed.