| 同步时序逻辑电路设计方法改进 |
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| 引用本文： | 陈玉明,胡继平,洪耀球.同步时序逻辑电路设计方法改进[J].景德镇高专学报,2005,20(4):28-29. |
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| 作者姓名： | 陈玉明 胡继平 洪耀球 |
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| 作者单位： | 景德镇高专,江西,景德镇,333000 |
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| 摘 要： | 用卡诺图化简法求电路激励方程的方法进行改进。
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| 关 键 词： | 卡诺图 激励方程 次态方程 状态表 状态图 |
| 文章编号： | 1008-8458（2005）04-0028-02 |
| 收稿时间： | 2005-09-10 |
| 修稿时间： | 2005-09-10 |
Improvement of Design Methods in Sychronous Time sequence Logic Circuit |
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| CHEN Yu-ming,HU Ji-ping,HONG Yao-qiu.Improvement of Design Methods in Sychronous Time sequence Logic Circuit[J].Jingdezhen Comprehensive College Journal,2005,20(4):28-29. |
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| Authors: | CHEN Yu-ming HU Ji-ping HONG Yao-qiu |
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| Institution: | Jingdezhen Ceramic Institute, Jiangxi ,333001, China |
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| Abstract: | This article introduces the current condition of network security and the concept of network security menace. It puts forward a safe IP network model, which is composed of four technique components, safe identification , safe transmission, safe recovery and safe watch. This article analyses each of the components thoroughly in order to ensure that the IP network model is safe. |
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| Keywords: | IP network safe identification safe transmission safe recovery safe watch |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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