| DDR2 SDRAM控制器的FPGA实现 |
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| 引用本文： | 须文波,胡丹. DDR2 SDRAM控制器的FPGA实现[J]. 江南大学学报(自然科学版), 2006, 5(2): 145-148 |
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| 作者姓名： | 须文波 胡丹 |
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| 作者单位： | 1. 江南大学,信息工程学院,江苏无锡,214122
2. 江南大学,信息工程学院,江苏无锡,214122;中国科学院,计算技术研究所,北京,100080 |
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| 摘 要： | 龙芯SoC第一版本(ICT-E32)中集成的是SDRAM控制器,但鉴于SDRAM性能的限制,使其成为提高龙芯SoC性能的瓶颈.为了进一步提高龙芯SoC性能,在新一款中集成了DDR2控制器.因为DDR2采用了新技术,使其实现相对于SDRAM更为复杂,因此预先在FPGA上对其进行实现,以方便对其在整个SoC设计中的集成.目前,该控制器已经通过功能仿真,并在Xilinx公司的Virtex-4系列FPGA上得以实现.
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| 关 键 词： | 龙芯SoC 现场可编程逻辑门阵列 第二代DDR同步动态内存 |
| 文章编号： | 1671-7147（2006）02-0145-04 |
| 收稿时间： | 2004-12-09 |
| 修稿时间： | 2005-01-13 |
Implementation of DDR2 SDRAM Controller in a FPGA |
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| XU Wen-bo,HU Dan. Implementation of DDR2 SDRAM Controller in a FPGA[J]. Journal of Southern Yangtze University:Natural Science Edition, 2006, 5(2): 145-148 |
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| Authors: | XU Wen-bo HU Dan |
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| Affiliation: | 1. School of Information Technology, Southern Yangtze University, Wuxi 214122,China; 2. Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080,China |
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| Abstract: | DDR2 SDRAM offers higher performance and clock frequency than DDE SDRAM.Godson SoC,ICT E32,integrates a SDRAM Controller,which becomes a bottle neck of performance improvement because of the limitation of its manner.To get a high point,we are willing to use a DDR2 Controller in the next Chip.Because of DDR2's new features,it is more difficult to be implemented than SDRAM.We firstly design it in a FRGA,then,it will be easy to be integrated in a SoC.Now,it is implemented in a Xilinx Virtex 4 FPGA,and the design has passed the function simulation. |
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| Keywords: | godson SoC FPGA DDR2 SDRAM |
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