一种两级CMOS运算放大器电源抑制比提高技术

在解释了传统基本两级CMOS运算放大器低电源抑制比(PSRR)原因的基础上,提出了一种简单电路技术来提高传统基本两级CMOS运算放大器中频PSRR.该方法原理是通过改变偏置结构产生一个额外的信号支路在输出端跟随电源增益,这样在输出端可以得到近似为零的电源纹波增益,从而能提高运放的PSRR.采用0.35μm标准CMOS工艺库,在Cadence环境下仿真结果显示,改进的运算放大器的PSRR在中频范围内比传统运算放大器可提高20 dB以上.

PSRR improvement technique for two-stage CMOS operational amplifier

On the basis of explaining low power-supply rejection ratio (PSRR) of the traditional basic two-stage CMOS operational amplifier (op-amp), a simple circuit technique is presented for improving poor midband PSRR of the traditional basic two-stage CMOS single ended op-amp. The principle of the technique is to create an additional parallel signal path to follow signal gain from the power-supply to the output by means of changing the bias structure, which produces almost zero power-supply ripple gain through the output stage and improves the PSRR. Cadence simulation results of a proposed two-stage op-amp based on standard 0.35 μm technology show that more than 20 dB improvement in the midband PSRR is obtainable compared with a traditional basic two-stage op-amp without the suggested circuit.