| 一种基于多级流水线加法器的累加电路设计研究 |
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| 引用本文： | 袁松,唐敬友,刘莉. 一种基于多级流水线加法器的累加电路设计研究[J]. 四川理工学院学报(自然科学版), 2012, 25(5): 50-53 |
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| 作者姓名： | 袁松 唐敬友 刘莉 |
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| 作者单位： | 1. 西南科技大学 理学院
2. 西南科技大学国防学院,四川绵阳,621010 |
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| 摘 要： | 专用硬件电路常用来实现加速,以提升科学计算速度。在科学计算中,多个数据的累加是常见运算。在设计硬件累加器时,容易出现流水线阻塞问题。提出将数据依据流水线级次分成两类模块,不同类型的模块采用不同的累加方式。基于多级流水线加法器,在FPGA上实现了多个数据的累加。该设计消耗资源少,流水线利用率高,控制相对简单,尤其是在数据规模很大时,优势尤其明显。
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| 关 键 词： | 硬件加速 FPGA 多级流水线 累加器 |
Research on a Kind of Accumulator Basing on Multilevel Pipeline Adder |
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| YUAN Songa,TANG Jing-youb,LIU Li. Research on a Kind of Accumulator Basing on Multilevel Pipeline Adder[J]. Journal of Sichuan University of Science & Engineering(Natural Science Editton), 2012, 25(5): 50-53 |
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| Authors: | YUAN Songa TANG Jing-youb LIU Li |
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| Affiliation: | a (a.School of Science;b.School of National Defense,Southwest University of Science and Technology,Mianyang 621010,China) |
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| Abstract: | Purpose-designed circuits can accelerate the speed of scientific calculation.Multiple data accumulation is a common operation in scientific calculation.It is easy to meet pipeline data hazards during designing the hardware accumulator.Our design is dividing those data into two kinds of modules according to pipeline level,and different modules using different accumulation methods.Based on a multilevel pipeline adder,this design is implemented on a FPGA.It has less hardware resources and higher pipeline utilization,and the control is relatively simple.Especially for large-scale data,its advantages can be fully taken on. |
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| Keywords: | hardware acceleration FPGA multilevel pipeline accumulator |
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