| TD-SCDMA下行同步算法设计与FPGA实现* |
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| 引用本文： | 喻勇,田增山,周牧. TD-SCDMA下行同步算法设计与FPGA实现*[J]. 科学技术与工程, 2014, 14(7): 201-205 |
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| 作者姓名： | 喻勇 田增山 周牧 |
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| 作者单位： | 重庆邮电大学移动通信技术重庆市重点实验室,重庆邮电大学移动通信技术重庆市重点实验室,重庆邮电大学移动通信技术重庆市重点实验室 |
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| 基金项目： | 国家自然科学基金(61301126),重庆市基础与前沿研究计划项目(cstc2013jcyjA40041),重庆邮电大学博士启动基金(A2012-33),重庆邮电大学青年科学研究项目(A2012-77)。 |
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| 摘 要： | 针对TD-SCDMA系统下行同步快速高效需求,在分析TD-SCDMA物理帧结构的基础上,提出了一种利用功率比检测作为粗同步,并结合频域相关确定精确同步的TD-SCDMA下行同步算法与FPGA实现方案。利用Modelsim和Matlab对算法的可行性和有效性进行了仿真验证。最后在Altera Cyclone III FPGA硬件平台进行了板级调试和实时数据验证。结果表明该同步算法具有较好的实时性和较高的稳定度。
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| 关 键 词： | 同步 TD-SCDMA 功率比检测 FPGA |
| 收稿时间： | 2013-09-18 |
| 修稿时间： | 2013-10-27 |
Design and Implementation of TD-SCDMA Downlink Synchronization Algorithm Based on FPGA |
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| Yu Yong,Tian Zengshan and Zhou Mu. Design and Implementation of TD-SCDMA Downlink Synchronization Algorithm Based on FPGA[J]. Science Technology and Engineering, 2014, 14(7): 201-205 |
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| Authors: | Yu Yong Tian Zengshan Zhou Mu |
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| Affiliation: | Chongqing Key Lab of Mobile Communications Technology,School of Communication and Information Engineering,Chongqing University of Posts and Telecommunications,Chongqing Key Lab of Mobile Communications Technology,School of Communication and Information Engineering,Chongqing University of Posts and Telecommunications |
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| Abstract: | By the requirements of high-speed and efficient downlink synchronization in TD-SCDMA system, and also based on the analysis of physical frame structure of TD-SCDMA, this paper proposes a downlink synchronization algorithm and related FPGA implementation approach for TD-SCDMA system. We first rely on the power ratio detection to conduct the coarse synchronization, and then use the frequency domain correlation to realize the precise synchronization. Moreover, the Modelsim and Matlab are utilized to verify the feasibility and effectiveness of our proposed algorithm. Finally, with the help of the board debugging and real-time data examination on Altera Cyclone III FPGA chip, it is also demonstrated that our synchronization algorithm can provide well real-time performance and high degree of stability. |
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| Keywords: | synchronization TD-SCDMA power ratio detection FPGA |
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