基于四值逻辑的伽罗华域AB+C电路设计

为了提高AB+C运算电路的运算速度,降低其电路实现的复杂性,本文在GF(2⁴)上给出了一种基于四值逻辑的AB+C算法及其基于脉动阵列结构的电路实现.在电路设计中采用了基于源极耦合逻辑的多值技术,利用四值电流模进行运算,以改善电路的首次延时及晶体管和连线的数目.在0.18μm CMOS工艺下利用HSPICE进行了电路仿真验证.结果显示,对比于相应的基于二值逻辑的COMS实现技术,首次延时及晶体管与连线的数目总和分别减少了54%和5%.所设计的并入并出脉动阵列电路,结构简单、规整、模块化,适用于VLSI的实现.多值逻辑电路与基于多值逻辑的对应算法的结合很可能成为实现GF(2^k)上高性能运算的潜在解决方案.

AB+C Circuits Design in Galois Fields Based on Quaternary Logic

In order to reduce the long latency and circuit complexity, a quaternary algorithm of AB+C and its implementation were presented based on systolic array structures in GF(24). The systolic structure was arranged to employ a quaternary logic technique based on dynamic source-coupled logic to do arithmetic operations, to use current-mode signals to decrease the initial delay, transistors and wires. A simulation evaluation was carried out with a 0.18 μm CMOS technology. The results show that, compared with the corresponding binary CMOS implementations reported in references, the initial delay and the sum of transistors and wires in this design can be reduced about 54% and 5%. The parallel-in parallel-out systolic structure proposed is simplicity, modularity and scalability, being suitable for VLSI implementations. The scheme of combining multiple-valued circuits and corresponding algorithms based on multiple-valued logic (MVL) is expected to be a feasible alternative for super performance arithmetic units in GF (2k).