| EDA在数字频率计中计数模块里的应用 |
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| 引用本文： | 彭惠芹. EDA在数字频率计中计数模块里的应用[J]. 华北科技学院学报, 2010, 7(1): 73-75 |
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| 作者姓名： | 彭惠芹 |
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| 作者单位： | 山西大同大学,工学院,山西,大同,037003 |
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| 摘 要： | 计数模块是数字频率计系统的核心模块,频率测量的主要工作由它来完成.本文根据数字频率计的特点,在Altera公司的FPGA开发平台QuartusⅡ中实现,同时采用VHDL硬件描述语言,提出了一种实用性较强的计数模块的设计方案.
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| 关 键 词： | 数字频率计 CPLD技术 计数模块 自顶向下方法 VHDL语言 |
The application of EDA on the counter module in Digital frequency counter |
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| PENG Huiqin. The application of EDA on the counter module in Digital frequency counter[J]. Journal of North China Institute of Science and Technology, 2010, 7(1): 73-75 |
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| Authors: | PENG Huiqin |
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| Affiliation: | School of Engineering;Shanxi Datong University;Datong Shanxi 037003 |
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| Abstract: | The counter module is the kernel modules of Digital frequency counter.The frequency measurement of the major tasks to be completed by it. According to Digital frequency counter's characteristic ,the text is realized on the Quartus II of FPGA in the company Altera.Modules using VHDL language to describe. Proposed one usable strong counter module design. |
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| Keywords: | Digital frequency counter EDA technology counter module top-down VHDL language |
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