一个实用的VLSI电路故障模拟器

在集成电路的计算机辅助设计过程中,故障模拟是验证、产生测试码和生成故障字典的重要部分。本文介绍了VLSI-CAD系统中的故障模拟系统,该模拟系统采用同时模拟的方法。模拟的对象为以晶体管级、门级、功能级描述的电路。除了用标准库中逻辑元件定义的电路外,还允许用户自己定义功能块或子电路。在算法的实现上,对超故障表的运算和存贮单元的分配采取了合理的处理方法。该系统是在VAX-11/750机上用C语言实现的。实践的结果表明,该系统具有通用性强、效率高、容易扩充逻辑元件和信号状态等优点,是一个可用于VLSI电路的实用系统。

A Practical Fault Simulator for MOS VLSI Circuits

In the computer-aided design of integraed circuits, the faultsimulator is an important tool to verify the quality of test patterns andto generate test patterns and the fault dictionary. This paper describes afault simulator for the VLSI-CAD system developed at SJTU. In the presentfault simulator, a concurrent algorithm is used. The circuit networks to besimulated are described at transistor, oate and functional levels. Usersdefine the functional blocks and subcircuits, as well as the circuit networkusing the logic elements in a built-in library. In the implementation of thealgorithm, a rational method for the operation of super fault lists and theallocation of memory areas is adopted. The fault simulator is implementedon VAX-11/750 in C. The experiments show that the simuator has the advant-ages of generality, high efficiency, and facility in etending the logicelements and the signal states. Hence it is a practical software systemapplicable to the VLSI circuit.