一种高速浮点信号处理机的结构及其语言的设计与实现

脉动阵列体系结构(systolic array architecture)是70年代末出现的一种新的并行计算机结构,这种计算机结构简单并且可以获得很高的处理速度,在许多应用领域中有着广阔的发展前景。本文介绍了一种基于脉动阵列结构的高速浮点信号处理机。该处理机由16个处理单元和一个高速缓冲存储器组成一个一维线性阵列。每个处理单元都是可编程的浮点处理器,其最大处理速度为20MFLOPS,因此该处理机(16个处理单元)的峰值处理速度为320MFLOPS。该处理机以一种外部设备方式与主机的VME总线相连接。 本文还介绍了该机所使用的并行语言,以及该语言编译程序的设计与实现。这种语言结构简单,编程容易,程序的结构清晰,易读。

A HIGH SPEED FLOATING POINT SIGNAL PROCESSING MACHINE: ARCHITECTURE, LANGUAGE AND COMPILER

Systolic array architecture, a new type of parallel computer architecture, appeared in the late 1970s. The architecture, regular and simple, can gain very high speed, so it will be widely used in many fields. This paper describes a computer based on the systolic arrary architecture, handling floating point signal at high speed. It consists of 16 cells and a cache connected linearly. Each cell is a programmable processor capable of performing 20 million floating point operations per second (20 MFLOPS). The machine therefore has a peak performance of 320 MFLOPS. It is integrated as an attached processor into a VME bus host system. The B lan-guage used by the computer and the realization of the B language compiler are also described.