基于FPGA查阅表的面向结构的逻辑优化

介绍了基于现场可编程门阵列（ＦＰＧＡ）查阅表的逻辑优化准则．基于这一准则，讨论了几种重要的逻辑优化运算，例如抽取、分解、约数检查和简化，以按照目标工艺技术估算电路的价格．基于ＦＰＧＡ，利用我们的方法对查阅表进行逻辑优化，可以得到工艺映射中的良好出发点．以２５个基准试验例子为基础，我们的优化电路所需要的构造逻辑方块（ＣＬＢ）比利用ＭＩＳ－ＩＩ的优化电路的情形下少百分之十四，如果两者都利用ＭＩＳ－ｐｇａ顺序映射的话．此外，电路的级数也稍有改进．

Architecture Oriented Logic Optimization for Lookup Table Based FPGAs

A logic optimization criterion for lookup table based Field Programmable Gate Arrays (FPGAs) is presented. Based on this criterion,several key operations of logic optimization,such as Extraction,Decomposition,Resubstitution and Simplificaton,are discussed so as to make them evaluate the circuit cost in accordance with the target technology.Using our opproaches to do logic optimization for lookup table based FPGAs,we obtain a good starting point for technology mapping. On the basis of 25 benchmark examples,our optimized circuits require 14% fewer CLBs than the circuits optimized by MIS-II if both are subsequently mapped using MIS-pga. Moreover,the number of circuit levels is also slightly improved.