| 基于FPGA的神经网络硬件实现中的关键问题研究 |
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| 引用本文： | 张秀艳.基于FPGA的神经网络硬件实现中的关键问题研究[J].科技情报开发与经济,2005,15(5):273-275. |
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| 作者姓名： | 张秀艳 |
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| 作者单位： | 中北大学,山西,太原,030051 |
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| 摘 要： | 对基于FPGA的神经网络硬件实现系统中的两个关键问题——约束和下栽配置进行了研究，以Xilinx公司生产的Virtex-Ⅱ系列FPGA器件作为目标器件，给出系统的约束设计方案及下栽配置硬件电路，经过静态时序分析，约束设计符合要求，下栽配置电路设计合理。
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| 关 键 词： | FPGA 神经网络 时序 约束 下栽配置 |
| 文章编号： | 1005-6033(2005)05-0273-03 |
| 修稿时间： | 2004年12月7日 |
Research on the Key Problems in FPGA -based Neural Network Hardware Implementation |
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| ZHANG Xiu-yan.Research on the Key Problems in FPGA -based Neural Network Hardware Implementation[J].Sci-Tech Information Development & Economy,2005,15(5):273-275. |
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| Authors: | ZHANG Xiu-yan |
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| Institution: | ZHANG Xiu yan |
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| Abstract: | This paper studies the two key problems in FPGA-based neural network hardware implementation, the constriction and download configuration, taking Virtex-II series devices of FPGA produced by Xilinx Company as the target devices, describes the constriction design scheme and the download configuration hardware circuit of the system, and through static timing analysis, points out that the design of constriction fits in with the requirements and the download configuration circuit is rational. |
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| Keywords: | FPGA neural network time series constriction download configuration |
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