基于多相位量化噪声抑制的分数频率合成器的实现

为抑制Σ-△调制器量化噪声对分数频率合成器输出噪声的影响,提出一种基于多相位分数分频器的频率合成器结构. 该结构可以避免毛刺并且主要电路模块不需要工作在高频,从而相应节省了功耗,同时分频器的输入可以不需要50%的占空比. 通过对比发现,对于环路带宽为1 MHz的宽带情况下的Σ-△分数频率合成器,多相位分频器技术可以减小频率合成器输出频谱的相位噪声达12 dB. 该频率合成器使用UMC 0.18 μm CMOS工艺实现,仿真结果证明它可以满足DVB-H系统协议指标要求. 

Quantization Noise Suppression of Fractional-N Frequency Synthesizer Based on Multi-Phase Frequency Divider

To suppress the quantization noise from Σ-△ modulator,this paper proposed a frequency synthesizer based on multi-phase fractional divider. This structure can avoid glitch while consuming less power because all main block working on lower frequency. 50% duty cycle input also does not needed here. Through comparing, this technique can reduce 12 dB output phase noise of a 1 MHz bandwidth Σ-△ fractional-N frequency synthesizer. This synthesizer is implemented in UMC 0.18 μm CMOS process, the post-layout simulation shows that it can meet the requirement of DVB-H system.