跳频系统中Turbo码译码器的FPGA实现

给出了跳频系统中Turbo码译码器的FPGA(field programmable gate array)实现方案.译码器采用了Max-Log-Map译码算法和模块化的设计方法,可以对不同帧长的Turbo码进行译码.在Xilinx公司的FPGA芯片xc3s2000-4fg676上实现了帧长可变的Turbo译码器.在帧长为1 024 bit、迭代5次条件下,该译码器时延为0.812 ms,数据吞吐量为1.261 Mbit/s.分别在高斯白噪声和部分频带噪声干扰两种信道环境中测试该Turbo码译码器的误码率性能,在部分频带噪声干扰中使用了AGC(自动增益控制),结果表明,AGC有效提高了译码器在部分频带噪声干扰下的性能.

FPGA Implementation of Turbo Decoder in Frequency-Hopping System

Implementation scheme of FPGA(field programmable gate array) Turbo decoder is presented.Max-Log-Map algorithm and modular design methodology is employed and the decoder is able to decode variable length Turbo codes.A Turbo decoder with variable packet length has been implemented in a Xilinx xc3s2000-4fg676 FPGA circuit.Under the condition that packet length is(1?024?bit) and iteration times is 5,the throughput of the decoder is 1.261?Mbit/s and decoding latency is 0.812?ms.The designed Turbo decoder is tested under additive white Gaussian noise and partial-band noise interference channel for its bit error rate performance.AGC(adaptive gain control) is employed under partial-band noise interference channel.Simulation results showed that performance of the decoder is improved with AGC.